IRL1206FI

Core:

• 32-bit BM-310S0 RISC-V core with RV32IMCNZX instruction set;
• Clock frequency up to 50 MHz for IRL1206FI (CHIP_ID = 217);
• Performance of up to 3.70 CoreMark/MHz when executing from integrated TCM memory;
• Performance of up to 2.15 CoreMark/MHz when executing from Flash memory for IRL1206FI;
• Two-cycle multiplication;
• Instructions for accelerating cryptographic algorithms such as Streebog, Magma, SHA2, AES, etc.;
• Physical memory protection hardware.

Operating characteristics:

• Temperature range: minus 50°C plus 85°C
• External power supply:
  
  
  • 3.0 to 3.6 V (with AFE);
  • 1.8 to 3.6 V (without AFE);

Memories:

• On-chip non-volatile Flash program memory with a capacity of 2×256 KB (main area) + 2×8 KB (information area);
• On-chip RAM with a capacity of 112 KB.

Clock system:

• Internal 6 to 10 MHz oscillator;
• Internal 32 kHz crystal oscillator;
• External oscillator, 8 to 16 MHz;
• External oscillator, 32 kHz;
• On-chip PLL clock frequency multiplier for the core.

Low-power mode:

• Battery domain including real-time clock, calendar, three tamper detectors and 512 bytes of RAM.

Analog peripherals:

• 24-bit ΔΣ ADC (seven independent channels with a programmable gain amplifier (PGA));
• 10-bit ADC (three external multiplexed channels and an internal temperature sensor channel).

Digital peripherals:

• Direct memory access controller with Peripheral-to-Memory, Memory-to-Memory transfers;
• Interface controllers: 4 × UART, 3 × SSP, 1 × I2C, 1 × ISO7816;
• Random number generator;
• Protection grid, power supply voltage detectors;
• Up to 55 user-defined IO lines;
• Four 32-bit timer blocks with four event capture channels and a pulse-width modulation (PWM) block;
• Two watchdog timers;
• CRC calculation block with a configurable polynomial.

Debug mode:

• Serial debug interface (JTAG).